In packet communication systems it may be advantageous to have the ability to send data at the full rate that an interface can support. These systems usually contain several data path elements which must transfer packets from one element to another element, each element having its own local packet buffer(s). When these data path elements are connected with shared busses the latency of transferring data packets between the elements can become long and variable, thus making it difficult for the sender of packets to know how much buffer space the receiver has left.
In circumstances where flow control data is to be transferred over this type of variable latency interface the problem may be compounded since the sender device does not know whether the last flow control data received from the receiver device corresponds with the last packet data transmitted by the sender. This can result in overflows (e.g., resulting in lost packets) and underflows (e.g., resulting in under utilization) of the receiver's buffers.
It will be appreciated that this may particularly be a problem in communications systems where a central processing unit (CPU) with large memory buffers sends data to a communication device with relatively smaller memory buffers. In such systems the CPU will need to estimate the capacity of the receiving communication device's buffer to assure that it does not overflow with transmit packets. In systems with the possibility of long latencies, the CPU will need to go into a transmitter ‘off’ state or XOFF state (e.g., buffer full) before the packet receiving device has actually sent an XOFF command. Variable latency may further result in edge cases where the receiving device does not go into an XOFF state as expected but remains in transmitter ‘on’ or XON state (e.g., buffer not yet full), since its buffers may have cleared before the packet that was expected to turn it XOFF arrived.